White Paper: Ultra3 SCSI: The next industry standard

Ultra3 SCSI promises data throughput of up to 160Mb/s along with full backward compatibility

Ultra3 SCSI promises data throughput of up to 160Mb/s along with full backward compatibility

On September 14, 1998, seven vendors, representing a broad cross-section of the computer system and storage industry, announced support for evolutionary changes to the Small Computer System Interface (SCSI) that increases performance, reliability and manageability. Ultra3 SCSI doubles transfer rates from 80 to 160Mb per second, improves manageability by automatically testing the interfaces performance level and increases reliability by adding Cyclical Redundancy Checks (CRC). When Ultra3 SCSI is used with low-voltage differential (LVD) signalling, cable lengths of 12m are maintained providing full backward compatibility.

The SCSI technology continues to evolve and its evolution is successfully meeting the increasing demand for I/O bandwidth. The SCSI interface has the stability, ease of connectivity, large installed base and a 15-year heritage offering full backward compatibility. The new implementation of SCSI boosts performance, reliability and manageability even more.

The ANSI standards T10 committee is revising the SCSI Parallel Interface (SPI-3). This document is the basis of the Ultra3 SCSI technology. Evolutionary changes have been made to the existing SCSI protocol (SPI-2) to increase performance, manageability and reliability. All changes are incremental and existing SCSI protocols are maintained for backward compatibility. Three new underlying components of Ultra3 SCSI are Double Transition Clocking, Cyclical Redundancy Checks (CRC) and Domain Validation.

Ultra3 SCSI doubles transfer rates to 160Mb per second by using both edges of the request/acknowledge signal to clock data. This creative solution provides designers with the choice of improving speed, reliability or connectivity. It allows system designers to choose bus bandwidths up to 160Mb/s using existing Ultra2 SCSI cable plants. Alternatively, this technology lets designers maintain Ultra2 SCSI speeds (80Mb/s) and improve reliability by lowering clock speed, allowing more margin for ASICs and cables.

Other Ultra SCSI improvements include automatic tests of the interfaces performance level for increased manageability and the addition of CRC for reliable data transmission. When Ultra3 SCSI is used with LVD signalling, cable lengths of 12m are maintained providing full backward compatibility.

Double Transition Clocking (DTC) changes the digital protocol to use both edges of the SCSI request/acknowledge signal to clock data. Data transfer rates can be doubled simply by increasing the speed of only the data lines. For example, request / acknowledge signal on Ultra2 SCSI runs at 40MHz, while data runs at only 20 MHz or 80Mb/s on a 16-bit wide bus. By using both edges of the same 40MHz request / acknowledge signal, the data rate can be increased to 40MHz, or 160Mb/s on a 16-bit wide bus.

DTC doubles the Ultra2 SCSI data transfer rates from 80Mb/s to 160Mb/s. Interface bandwidth is an essential ingredient for Windows NT and UNIX workstations, video and web servers, and Storage Area Networks (SANs).

DTC keeps the maximum clock rate at half the rate of single edge clocking. This provides more timing margin for ASICs, cables, motherboard traces, high capacitance devices, extra connectors and so forth. Longer pulses reduce the likelihood of problems by increasing timing margins and tolerance to noise. DTC reduces the maximum frequency of the clock lines (REQ/ACK) without slowing the data rate. Slower clocks should also reduce EMI issues for system designers.

The Ultra SCSI reliability enhancements include the addition of a Cyclical Redundancy Check (CRC) on customer data. CRC provides extra data protection for marginal cable plants and external devices, and is one of the best ways to assure data protection during hot plugging. CRC offers higher levels of data reliability by ensuring complete integrity of transferred data. It dramatically reduces undetected error rates by using the same proven CRC that is utilised by FDDI, Ethernet and Fibre Channel interface.

The Ultra3 SCSI CRC detects all single bit errors, all double bit errors, all odd number of errors, all burst errors up to 32-bits long and has an approximately 2-32 rate of undetected random error patterns. The third component of Ultra3 SCSI is Domain Validation. This technology intelligently tests storage networks including cables, backplanes, terminators, expanders, bridges and so forth. Domain Validation ensures that the network is operating at the required specifications. If reliability is at risk, the transfer proceeds without a hitch at a lower speed much the way today's modem and fax transmissions connect despite variations in equipment.

Domain Validation should increase end-user satisfaction and decreases total cost of ownership by reducing service calls for under performing systems. In addition, these tests could save on call center support resources and help alleviate end-user frustration

In the past, new devices such as host bus adaptors (HBAs) and hard disk drives (HDDs) did not always work smoothly with legacy configurations. Domain Validation helps assure that Ultra3 SCSI devices operate smoothly in existing legacy systems. This testing is done automatically without changing controller settings, setting BIOS parameters or fumbling with manuals.

The rule of thumb for the past 15 years has been that bus bandwidth should be at least four times the maximum throughput of a drive. The Ultra3 SCSI bus bandwidth should stay comfortably ahead of the internal transfer rates of the next generation 10K HDDs expected in 1999. These HDDs can saturate the Ultra2 SCSI bus with as few as three drives.

SCSI has a 15-year heritage of maintaining full backward compatibility and excellent forward compatibility. About every two years small evolutionary changes are made to this standard to improve speed, reliability and manageability. The low risk upgrade to Ultra3 SCSI is the next natural transition.

Compiled by Ajith Ram

(c) 1999 Quantum

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