Intel shows off 65-nanometer memory cells


Intel shows off 65-nanometer memory cells

Intel has demonstrated working SRAM (static RAM) chips with transistors built using the company's 65-nanometer process technology.

Microprocessors built using the technology will be ready in 2005, the company said. Intel uses SRAM chips to test out its process technology because the chips are easy to design and troubleshoot, but the transistors will be used on new versions of products such as the Pentium 4 or Xeon, said Mark Bohr, director of the company's process architecture and integration.

Products built on Intel's 90-nanometer process technology are expected to make their debut in the coming weeks. For the next generation of chips built at 65 nanometers, Intel will keep the strained silicon and copper interconnects used in 90-nanometer chips, Bohr said.

Strained silicon is a manufacturing technique in which a layer of silicon germanium is deposited on top of a silicon wafer. The atoms in each substance naturally seek to align themselves, which stretches the silicon, allowing more electrons to flow than was possible with just silicon.

Tom Krazit writes for IDG News Service.



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