Today, a large-scale, chip fabrication plant costs a staggering $1.5 billion dollars to build. Within the next decade - as new technologies emerge to reduce structure dimensions below 0.1 microns (a hundredth the thickness of a human hair) and create ultra-complex chips, populated with hundred of millions of transistors - the cost of a fabrication plant will skyrocket towards $10 billion.The laws of physics are constantly being stretched in the relentless pursuit of putting more power and functionality into smaller and smaller chips that cost less and less to manufacture. Despite the huge capital investment in fabrication facilities, the wafer-thin products churned out in their millions from such plants have a product cycle time measured in just months. With such huge financial investments at stake and such small windows of opportunity for each new chip, the pressures on integrated circuit designers are immense. The direct cost for each day that a plant stands idle, waiting for a new chip design to be completed, is measured in hundreds of thousands of dollars. The indirect cost in lost sales and lost market opportunity is incalculable. Only a handful of the very largest and most efficient chipmakers will be able to compete in this league. One of the most profitable, innovative and productive of these is the $4.5 billion Siemens Semiconductor business. Based in Munich, and with fabrication facilities all over the world, Siemens Semiconductor is a global leader in the development and manufacture of 64Mb and 256Mb Dynamic Random Access Memory chips used in modern PCs, workstations and servers. The company is also a large producer of more sophisticated chips that combine standard memory and custom logic in single microprocessors used to drive popular brands of video games, mobile phones, smartcards, automobile electronics and a host of other consumer electronic products. As with all chip manufacturers, the design teams at Siemens Semiconductor are squeezed between two seemingly conflicting pressures. On the one hand, market forces dictate that they generate ever more densely populated chips - designed for very low-cost, high-yield fabrication - and bring products extremely fast to market. On the other, the complexity rises exponentially, simply because the number of transistors packaged on a chip doubles every 18 months. This stretches the development cycle and escalates the verification run-times that are essential in ensuring absolute zero defects prior to fabrication. The final layout assembly and verification of a very complex chip can take approximately 20 days, mainly due to very long verification cycles. Reducing verification run-times therefore was a major challenge for Siemens Semiconductor. In the weeks immediately prior to the scheduled start of fabrication, designers would have to complete a lot of error correction and verification cycles on the entire integrated chip. Each verification run would take anything from 8 to 18 hours, which meant, at best, design engineers could only work within a daily cycle. "A 20-day verification cycle meant that the chip design had to be complete four weeks prior to fabrication, which it never was. And with technology advancing and chip designs becoming more complex, the verification run-times were getting even longer," said Wolfgang Grimm, CAD manager at Siemens' Memory Products Division. Major productivity improvements were required to deliver a meaningful impact. Small improvements to the verification cycles would produce little value. "The design teams needed to move from a daily, to half-day or even two-hour error correction and verification cycles. We could only achieve that by tackling three things: selecting the best verification tool; improving the verification rulesets; and installing the highest performing hardware platforms," explained Grimm. "Using the experience of our own engineers, coupled with Cadence's Vampire Software running on powerful SMP servers from Sun Microsystems, we have succeeded in reducing run-times of a full verification cycle dramatically to under one hour. All verification cycles can now be completed within one week, which means a new chip is three weeks earlier into fabrication and three weeks faster to market - an enormous business and financial benefit." As soon as the 200MHz Sun UltraSPARC became available, Sun Microsystems provided Siemens with a beta machine. By this time, the priority was to complete full verification of a new version of a 64Mb chip which was shortly due to enter fabrication. Being close to fabrication, the 64Mb project included all the requirements to maximise yield and achieve zero errors within the restricted period of time before the design had to be passed to the mask-house to prepare for production. Constantly pushing the performance curve, Siemens Semiconductor still considered the verification cycles to be too long. In the final stages, it became unproductive to have more than one or two design engineers verifying the complete integrated chip, so the CAD team turned to the processing hardware and Vampire MP software for further improvements. Verification software has to handle large volumes of data and very complex algorithms. The process is extremely resource hungry, requiring lots of memory, very fast disks and high-performance processors. The time problem is exacerbated because, during the final full-chip verification, there are three different types of design rule check (DRC), one for each of the three main types of cell area. In addition, the chip layout must also be compared back to the original design schematics using advanced Layout Versus Schematic software. To Jakobs, multiprocessing technology seemed the ideal solution for this problem. Conscious of the never-ending search within Siemens Semiconductor to improve performance, Sun Microsystems made available two Sun Ultra Enterprise 4000 servers. One server was for the Vampire software development team at Cadence and the other for benchmarking at Siemens Semiconductor. System engineers from Sun assisted both in tuning and in benchmarking. Using an early multiprocessor version of the Vampire software most DRC runs are completed faster on Sun SMP servers. Since the Solaris operating system is multithreaded and DRC runs are very I/O intensive, Solaris cuts down overall run-time by assigning different tasks to different CPUs. A single array DRC could be completed in just 24 minutes compared to 80 minutes on a single CPU. "It produced a very good performance improvement that took us within our one-hour target," Jakobs enthused. Compiled by Ajith Ram (c) 1994-1999 Sun Microsystems, Inc.