Engineers from Sun Microsystems will reveal the first technical details on the company's eight-core microprocessor, code-named Niagara, at the Hot Chips symposium at Stanford University in August.
Niagara will have eight processor cores, each of which will be able to perform four independent processing tasks, or threads, at the same time, Sun said. The chip will then break these threads into binary instructions that will be executed six at a time, thanks to a "single scalar six-stage pipeline", the company said.
Sun describes the chip as a low-power processor that will run at a relatively low frequency - perhaps in the 1GHz range - and will be optimised for web-based services.
"There are lots of threads, and those threads can be used efficiently by the short pipeline," Kevin Krewell, editor-in-chief of The Microprocessor Report, said.
Niagara's efficient use of power will come, in part, from the fact that it has only six pipeline stages. This is far fewer, for example, than Intel's latest Pentium processor, code-named Prescott, which contains 32 stages, Krewell said. "With the short pipeline stage, you are not wasting a lot of energy with lots of deep pipelining," he said.
The chip looks like it is being designed for web service providers such as Google, said Krewell. "Google's architecture might play well with this design with lots of processors in a dense package with relatively good power efficiency per processor," he said.
Texas Instruments recently began manufacturing the first Niagara chips, which are designed but not built by Sun.
Each of Niagara's processor cores will include a crypto co-processor, and each Niagara processor will have one floating point co-processor, as well as 3Mbytes of L2 cache.
The fact that Niagara will have one crypto co-processor for each of its eight cores, means that it will do well when performing security processing, for example sending and receiving information using the Secure Sockets Layer (SSL) protocol, Krewell said.
"Cache coherence is maintained by the L2 by means of a novel directory scheme, " Sun said. Niagara's on-chip memory controller can be used to access up to 32Gbytes of memory using four channels of DDR2 (Double Data Rate) memory interface over 20gbps of memory bandwidth, the company said.
Sun expects to begin shipping systems based on Niagara in early 2006. The presentation on Niagara is scheduled for 24 August.
Robert McMillan writes for IDG News Service
This was first published in June 2004