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IBM will create a "stripped-down version of the Power4" for the PowerPC market, said Kevin Krewell, senior editor of the Microprocessor Report and general manager at market research company In-Stat/MDR.
The 64-bit chip will use an eight-way superscalar pipeline, which allows the chip to process eight different instructions during a single clock cycle. The chip will be able to process data at up to 6.4Gbytes a second, and will contain a vector processing unit that can perform more than 160 specialised vector instructions.
Vector processing allows the same instruction to be applied to multiple units of data simultaneously, an advantage when working with graphics-intensive programs.
IBM confirmed the basic details of the chip but refused to comment further. Additional technical and availability details will be announced at the Microprocessor Forum in October, the company said.
IBM's new chip will have to target the Linux workstation market or Apple's PCs, because it uses a different architecture and instruction set than those PCs powered by the x86 instruction set in Intel and Advanced Micro Devices's chips, Krewell said.
Motorola manufactures the majority of chips used in Apple's PCs. IBM could also package the chip with Linux or AIX, its version of Unix, and sell its own workstations based on the technology.
However, the chip will probably start out in low-end servers, as the initial price could be prohibitive for desktop machines, Krewell said. It could also feature in blade servers but this will depend on the chip's heat dissipation characteristics, he added.
The clock speed of the chip will probably be about 1.6GHz to start, ramping up to 2GHz as IBM becomes more accustomed to the technology, Krewell said.
IBM and Motorola jointly developed the PowerPC based on proprietary RISC (reduced instruction set computing) technology. The PowerPC is used in networking equipment, such as routers and hubs, and in consumer devices such as set-top boxes and printers.