ClearSpeed Technology has doubled the performance of its high-performance computing co-processor for scientific workstations and server clusters.
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It has incorporated 96 separate processing cores on a single chip, the company said at the Fall Processor Forum.
The new CSX600 co-processor runs at 250MHz and can achieve 50G Flops (floating point operations per second), a significant improvement over the 200MHz CS301. The older chip produced 25G Flops of performance when added to workstations or servers through a PCI card.
Co-processors are used to relieve the general processors of mathematically intensive tasks that can sap overall system performance. By offloading those tasks to the CSX600, users can run specialised applications on their personal or workgroup machines instead of fighting with colleagues to schedule server or cluster time.
This performance was made possible by the 96 individual processing units on the CSX600, said Simon McIntosh-Smith, director of architecture at ClearSpeed. Each unit is a very long instruction word (VLIW) processor core that produces a great deal of output without using a lot of power, producing as much as 10G Flops per watt, he said.
Power consumption is a huge concern for any product that is designed to fit into an existing system or sit alongside a general-purpose processor on a motherboard.
ClearSpeed hopes that system designers will start to include the CSX600 in systems designed for the high-performance computing market, but the company initially will sell PCI-X cards for about $50,000 (£28,000) that contain two CSX600 processors and slide into existing workstations and servers based on the x86 instruction set.
The older PCI-X bus technology can be a bottleneck for overall performance. ClearSpeed chose that bus technology because it is so widely used, McIntosh-Smith said. Intel is trying to popularise a faster technology called PCI Express that should help remove some of those concerns as it appears in more servers and PCs, he said.
Software will need to be ported to take advantage of the co-processor's performance.
Tom Krazit writes for IDG News Service