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IBM combines transistors to speed wireless chips

IBM has developed a technique for building two different types of silicon transistors atop a single wafer. The company hopes it will boost the performance of communications devices.

The majority of transistors built since the mid-1980s used complementary metal-oxide semiconductor (CMOS) transistors. But in the earlier part of the history of computing, most chips used bipolar transistors, said Ghavam Shahidi, director of silicon science for IBM Research.

Bipolar transistors are very good at amplifying low noises, or picking up quiet signals in loud environments, Shahidi said. For that reason, they are still used in some communications chips, although in small quantities due to their rabid power consumption and high manufacturing cost.

CMOS transistors are less expensive to build, and handle the majority of the data processing tasks on communications chips. In order to improve the performance of communications devices, IBM sought to discover a way to include bipolar transistors on the company's thin silicon on insulator (SOI) wafers, Shahidi said.

IBM uses SOI technology in its chips, and Advanced Micro Devices has also implemented the technology on its Opteron and Athlon 64 processors.

SOI wafers have a thin layer of oxide applied to them as an insulating agent against power leakage, and help improve the performance of CMOS transistors. But bipolar transistors have historically required a thicker base than is needed by CMOS transistors, making them unsuitable for chips built from SOI wafers, Shahidi said.

IBM has now built bipolar transistors atop its thin SOI wafers in its development labs, and hopes to bring the technology to end user products within five years, Shahidi said.

Possible applications for this technology include smaller Global Positioning System devices or cell phones with enhanced video streaming, IBM said.

Tom Krazit writes for IDG News Service


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