The Itanium, code named Madison, is scheduled for release in mid-2003.
Current Itanium 2 processors run at 900MHz and 1.0GHz, and come with up to 3Mbytes of Level 3 on-die cache. Madison will double the amount of L3 on-die cache to 6Mbytes.
Larger amounts of on-die cache allows frequently repeated instructions to be stored in memory extremely close to the main processors, reducing the time the chip needs to process those instructions.
Intel will pack 410 million transistors onto a die with an area of 374mm squared. The chip will dissipate 130 watts, the same as the Itanium 2 processor.
The Itanium also features Intel's explicitly parallel instruction computing (Epic) architecture, which requires users to recompile their reduced instruction set computing (RISC) or x86 applications to run on the Itanium processor.
The new architecture has made IT managers wary about converting their systems to servers from Hewlett-Packard and Unisys, among others, with the Itanium processor.
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