AMD's dual-core Opteron processor will fit into the same
area as its single-core product, helping to hold down manufacturing
costs.
The dual-core Opteron will come with 1Mbyte of Level 2 cache for
each core and fit into the same chipsets used by single-core
Opteron chips. A chipset connects the processor to a system's
memory and I/O ports.
Each dual-core Opteron will consume no more than 95W under
maximum operating conditions, said Kevin McGrath, an AMD fellow and
manager of the Opteron processor architecture. This is slightly
more than the 89W specified as the maximum power consumption for
the generation of single-core Opteron chips.
The ability to keep the die size constant was as a result of
AMD's 90nm process technology, McGrath said.
AMD will introduce the dual-core Opterons at lower speeds than
current single-core Opterons, McGrath said. The fastest single-core
Opteron in its product lineup runs at 2.4GHz, and dual-core chips
could be expected to run at least 1GHz slower than similar
single-core chips, he said.
Frequency is still an important consideration when determining
the overall performance of a system, but dual-core designs allow
chip makers to conserve power with slower cores, said Barry Crume,
a director with AMD's server and workstation business unit.
Future versions of Opteron will adopt multiple core designs and
eventually move to multiple memory controllers, McGrath said.
As the company adds multiple cores it will need additional
memory controllers to feed those cores with enough data to ensure
the processor is running efficiently, Crume said. Changes in the
standard for memory will also require changes to the memory
controllers as DDR2 (double data rate) and DDR3 memory evolve, he
said.
By that time, AMD will also be working on processors for servers
containing more than eight processors, McGrath said.
AMD has only recommended Opteron for servers with eight
processors or less to date, but the company plans to bring the chip
into the "big iron" space usually occupied by more expensive
servers based on a Risc architecture.
Tom Krazit writs for IDG News Service