Toshiba produces first X architecture test chip

The X architecture can provide improvements in chip performance over the traditional grid-like Manhattan design by enabling chip designs with less wiring and fewer connectors between wiring layers, or vias, the X Initiative consortium said.

The technique is suitable for mass production of chips and the first production chips are expected in 2004.

The five metal-layer test chip was produced using a 90-nanometer process technology, which is the most advanced manufacturing process used to manufacture commercial chips today.

Compared with a chip of similar functionality using only Manhattan interconnects, the X Architecture implementation used 14% less total wire length for the interconnects between transistor gates and 27% fewer vias.

Future developments should enable the wiring on a chip to be reduced by more than 20% and the number of vias to be reduced by more than 30%.

The X Initiative is a consortium of more than 20 companies involved in the semiconductor business, including Toshiba, Matsushita, STMicroelectronics, Cadence Design Systems, Nikon and Leica Microsystems.

David Legard writes for IDG News Service