IBM has predicted that a chip it is developing with the University of Texas at Austin could produce supercomputer-like performance, reaching one trillion operations per second by the end of the decade.
The new Trips (tera-op reliable intelligently-adaptive processing system) architecture developed by researchers uses a technique called block-oriented execution. This allows the chip to process large chunks of information in parallel, rather than waiting for a sequence of instructions to finish before taking on the next batch.
The joint project will attempt to develop a processor with the Trips architecture and up to four processor cores. That chip is expected to contain 250 million transistors, and run at 500MHz.
Multicore designs are the future of supercomputer and server processors. IBM's Power4 already incorporates a dual-core design, and Sun Microsystems, Intel and Hewlett-Packard are planning multicore processors.
The collaboration hopes to show that a processor with the Trips architecture can scale up to a 10GHz, which would reach the one trillion operations per second goal. Modern supercomputers can process several trillion operations per second, but require hundreds or thousands of processors to reach those numbers.
Professors at the University of Texas hope to develop prototype chips by the end of 2005, and IBM Microelectronics is expected to take over volume production once the chips are ready.
Tom Krazit writes for IDG News Service