Samsung Electronics says it has developed the industry’s first 40-nanometer (nm) memory device to improve manufacturing efficiency and boost device performance.
The new 32 gigabit nonvolatile solid state memory (NAND) flash device is the first memory product to incorporate a Charge Trap Flash (CTF) architecture, a new approach to further increase manufacturing efficiency while greatly improving performance.
The new CTF-based NAND flash memory increases the reliability of the memory by sharply reducing inter-cell noise levels. Its simple structure also enables higher scalability which will eventually improve manufacturing process technology from 40nm to 30nm and even 20nm.
In each 32gbit device, the control gate in the CTF is only 20% as large as a conventional control gate in a typical floating gate structure.
With CTF, there is no floating gate. Instead, the data is temporarily placed in a “holding chamber” of the non-conductive layer of the flash memory composed of silicon nitride.
This results in a higher level of reliability and better control of the storage current.
The 32gbit NAND flash memory can be used in memory cards with densities of up to 64Gbytes. One 64Gbyte card can store over 64 hours of DVD resolution movies (40 movies) or 16,000 MP3 music files (1,340 hours).
The CTF design is enabled through the use of a TanOS structure comprised of tantalum (metal), aluminum oxide (high k material), nitride, oxide and silicon.
The use of a TanOS structure marks the first application of a metal layer coupled with a high k material to the NAND device. Samsung first revealed the TanOS structure in 2003.
The introduction of a 40nm manufacturing process for 32gbit NAND flash marks the seventh generation of NAND flash, which follows the New Memory Growth Theory of double-density growth every 12 months.
This theory was first promoted by Chang Gyu Hwang, president and chief executive of Samsung, in 2002.
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