ARM offers new protocol for more efficient chips

An improved set of rules for communication among the different parts of a chip, unveiled by ARM, could help make the chips in...

An improved set of rules for communication among the different parts of a chip, unveiled by ARM, could help make the chips in mobile phones and other devices smaller and faster.

ARM announced the AMBA 3.0, the update to its Advanced Microcontroller Bus Architecturespecification, with an added protocol, called AXI (AMBA Extensible Interface).

The protocol was designed to pave the way to the next generation of high-performance system on a chip (SoC) designs.

It was developed through collaboration with many major chip suppliers, including Hewlett-Packard, Qualcomm, Toshiba and Ericsson Mobile Platforms.

It is the successor to AMBA 2.0, introduced in 1999 and widely used in chips for mobile phones, PC hard disc drives, home networking equipment and many other products.

A SoC is a single processor that combines many different elements. AXI describes a way to make those elements communicate faster and more efficiently, allowing for SoCs of smaller size, less power consumption, higher performance or a combination of all three.

A key step that made this possible was an unidirectional channel architecture, in which all information flow on the chip is in one direction only, said Jonathan Morris, platforms programme manager at ARM.

For chip suppliers, this architecture makes it simple to design and test a new chip, Morris said. It also will let some companies move from many different types of internal buses on their chips to one design, lowering their development costs, he added.

For users of devices based on AXI, it is likely to mean faster chips. The new approach adds a slight latency, or delay, but pays off by allowing for a higher clock rate, he said.

AXI also lets a chip execute multiple transactions at the same time, which means a chip can handle more functions at once or that it can finish a task more quickly and then go to sleep, reducing power consumption.

The latest protocol should make it possible for embedded chips to process high-bandwidth streams of packets quickly, reducing the need for memory, according to Peter Glaskowsky, a principal analyst at In-Stat/MDR.

That will be necessary as networks get faster and devices have to handle richer applications such as multimedia, he said.

It becomes possible with internal data buses that can deal with data streams quickly and at a predictable rate, so the chip does not have to set aside data in a buffer.

Without more efficient buses, memory buffers would have to get bigger as network speeds go up. Those buffers are made up of transistors, which take up space and consume power on an SoC.

"A fast, predictable bus doesn't take up any more space on a chip than a slow, unpredictable bus," Glaskowsky said, whereas more memory does.

AXI is available to chip developers now through a free licence and can be downloaded from ARM's website at

Stephen Lawson writes for IDG News Service

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