The technology - called “through-silicon vias” - allows different chip components to be packaged much closer together for faster, smaller, and lower-power systems.
The IBM breakthrough enables the move from horizontal 2-D chip layouts to 3-D chip stacking, which takes chips and memory devices that traditionally sit side by side on a silicon wafer and stacks them together on top of one another.
The result is a compact sandwich of components that dramatically reduces the size of the overall chip package, and boosts the speed at which data flows among the functions on the chip, said IBM.
“This breakthrough is a result of more than a decade of pioneering research at IBM,” said Lisa Su, vice-president for the IBM Semiconductor Research and Development Centre. “This allows us to move 3-D chips from the 'lab to the fab' across a range of applications.”
The new IBM method eliminates the need for long-metal wires that connect 2-D chips together, instead relying on through-silicon vias, which are essentially vertical connections etched through the silicon wafer and filled with metal.
These vias allow multiple chips to be stacked together, allowing greater amounts of information to be passed between the chips.
The technique shortens the distance that information on a chip needs to travel 1,000 times, and allows for the addition of up to 100 more channels, or pathways, for that information to flow compared to 2-D chips.
IBM is already running chips using the through-silicon via technology in its manufacturing line and will begin making sample chips available to customers in the second half of 2007, with production in 2008.
The first application of the technology will be in wireless communications chips that will go into power amplifiers for wireless LAN and cellular applications.
3-D technology will also be applied to a wide range of chips, including those running now in IBM’s high-performance servers and supercomputers.
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