Texas Instruments is to sample a wireless product built with its 65-nanometer semiconductor manufacturing process technology in the first quarter of next year.
The company said it expected the new technology will reduce leakage power from idle transistors, such as when a mobile phone is in standby mode, by a factor of 1,000.
Multimedia devices and high-end digital consumer electronics, such as wireless handsets and digital cameras, are pushing semiconductor makers to develop ever smaller chips that are faster and use less power more efficiently. Texas is, initially, focusing its 65-nanometer efforts on wireless applications, with plans to introduce its SmartReflex dynamic power management technology at the 65-nanometer node in chips for that type of use.
The technology monitors circuit speed and adjusts voltage to meet performance requirements of the device being used, boosting battery life and decreasing heat production.
Texas intends to offer several "optimised 65nm recipes" for different products or applications by adjusting transistor gated length, threshold voltage, gate dielectric thickness or bias conditions, among other things. Its 65-nanometer design library will provide circuit designers with options across multiple different voltage transistors.
Three different ranges of 65-nanometer semiconductors will be on offer. A low power option will be for portable devices, such as 2.5G and 3G wireless handsets, digital cameras and audio players with multimedia functions.
The midrange will support digital signal processing products and the company's high-performance ASIC (application-specific integrated circuit) library for communication infrastructure products.
A high-end version, which will have transistor gates as short as 29 nanometers, will support applications such as Sun Microsystems' next-generation UltraSparc processor-based servers.
Intel is working on its 65-nanometer technology, and Sony and its subsidiary Sony Computer Entertainment Inc. have joined forces with IBM and Toshiba. Samsung also is working with IBM to develop techniques for making components that will use 65-nanometer and 45-nanometer CMOS process technology.
Nancy Weil writes for IDG News Service