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Intel links Xeon applications with MIC architecture

Cliff Saran

Intel is demonstrating its response to the growing interest in graphics processor unit (GPU) and field gate array (FGA) powered high-performance computing by showing how Xeon applications can be run on a supercomputer architecture.

At the International Super Computing Conference 2011 in Hamburg, the company is selling the merits of its software development platform, which enables applications developed for its mainstream Xeon processor to be moved onto its many integrated core (MIC) architecture. MIC aims to tackle the types of computationally intensive applications that would previously have required multimillion pound supercomputers.

Anthony Neal-Graves, vice-president of Intel Architecture Group, says MIC will deliver the performance to run complex code in parallel where cost and power usage are limited.

Intel is developing a 22nm fabrication, which will lead to chips containing 50 cores. Neal-Graves says the company is introducing tools to help developers make the most of such multicore systems by making parallelism easier.

The National Center for Supercomputing Applications (NCSA) in Illinois has been piloting two MIC systems. "We have been able to demonstrate the performance characteristics of the hardware," it said.

The NCSA has used the OpenMP programming model. Applications built using alternative architectures, such as field gate arrays (ie hard-wired), could be moved relatively easily onto the MIC architecture, according to Mike Showerman, technical programme manager at the NCSA innovation systems lab.


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