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Details of AMD's Hammer emerge at Hot Chips

Limited specifications of Advanced Micro Devices' (AMD's) forthcoming Hammer technology were revealed at the Hot Chips conference in California on Wednesday (21 August).

Details include the clock speed and die size of the Athlon version of the Hammer chips, according to an analyst note about the company. However, AMD is denying the accuracy of the information distributed by the analyst.

The desktop Athlon chip, codenamed Clawhammer, is expected to initially run at 2.5GHz Joe Osha, an analyst with Merrill Lynch, said. Osha said later that he deduced the clock size from information he got at the conference from his own sources and available materials and the speed was not revealed by AMD.

This is less than the clock speeds of chips from Intel due out on Monday and later this year, but AMD says its chips are based on a more efficient architecture, and can execute more instructions per clock cycle than Intel's.

However, AMD's rating system for its current seventh-generation Athlon chips might have to be reworked if the 2.5GHz clock speed is correct. The system uses internal benchmarks to rate the performance of the Athlon chips compared to chips of competitors. For instance, the Athlon XP 2600+, released Wednesday, runs at 2.133GHz, but is said to perform as well as or better than Intel's current top-end 2.53GHz Pentium 4.

A 2.5GHz Hammer chip would need to conform to a different ratings structure because its performance is likely to be well beyond AMD's current seventh-generation Athlon XP 2600+.

"AMD has certainly not set guidance for the Hammer. Jerry Sanders [AMD's founder and chairman of the board] has talked about entering around 2.0GHz, but we haven't set the clock speed officially, or the model number," said John Crank, brand manager at AMD.

AMD revealed this week that it is working with PC vendors to develop a rating system for PCs that takes into account factors other than the clock speed of a PC's processor. The rating system will be released as soon as the company determines a reliable performance metric, AMD said. The Athlon version of the Hammer technology is scheduled to be available near the end of this year.

AMD has managed to limit the increase in die size, or the surface area occupied by a chip, to only 2-3%, compared to similar x86-based chips, according to the research note. This small increase in die size only applies to 32-bit chips that are turned into 64-bit processors without any additional enhancements, Crank said.

For example, the server version of the Hammer technology, the Opteron chip, would not fall into that category, as it includes 3 HyperTransport nodes and uses on-chip memory, Osha said. This would increase the die size by more than 3%, he said.

Smaller die sizes increase the number of chips a chip maker can produce per silicon wafer, said Shane Rau, a senior research analyst at IDC. The more chips produced by manufacturers per silicon wafer, the lower the cost of each individual chip to end users, he said.

AMD has not disclosed officially the die sizes of the Hammer technology yet, Crank said, but will do so when the product is launched.

Osha also said that the Opteron chip will compete with Intel's Xeon server chips, not the higher-end Itanium chips. Itanium chips boast higher performance than other x86-based server chips, but are expensive and have had difficulty breaking into the high-end server market dominated by reduced instruction set computing chips from Sun Microsystems and IBM among others. By pricing the Opteron relative to the more profitable Xeon chip, AMD will attempt to make inroads into the low and mid-range server market, Osha said.

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