IBM triples transistor performance

IBM has successfully demonstrated a new technique for improving transistor performance, allowing it to build smaller, more...

IBM has successfully demonstrated a new technique for improving transistor performance, allowing it to build smaller, more powerful chips in the next decade, the company declared yesterday.

IBM researcher Huiling Shang said the company had discovered a way to use germanium to improve the flow of electrons through its transistor. A layer of strained germanium was applied directly to the channel of the transistor, or the area through which electrical current passes, to open up additional space for electrons within the channel.

According to Shang, transistors built with strained germanium should have three times the performance of conventional transistors.

Germanium has been used in smaller doses by several companies, including IBM, in an existing manufacturing technique called strained silicon. This involves placing a mixture of germanium and silicon next to a layer of pure silicon, which causes the silicon atoms to stretch to align themselves with the silicon germanium atoms. This opens a wider path that allows more electrons to flow through the circuit.

Shang said researchers had long known that germanium was a better conductor of electricity than silicon, but IBM was the first to figure out how to build higher concentrations of germanium into chips using conventional techniques. She added that the company had also worked out how to strain the germanium layer to improve performance further.

A by-product of zinc ore processing, germanium is a hard element with the same crystal structure as a diamond. It is a semiconductor with electrical properties between those produced by a metal and an insulator. Its use as a transistor was key in the advancement of solid-state electronics.

IBM will present more details on how it accomplished its feat with germanium at the 2004 International Electron Devices Meeting in San Francisco next week.

The technique gives chipmakers another resource to improve performance as shrinking the transistor becomes more difficult. Although the technique is still in the research stage, IBM believes it could be used on the 32-nanometer process generation, currently scheduled for introduction around 2013.

Chip designers have been improving performance for years by making transistors smaller and smaller. Smaller transistors are generally faster, and more of them can be fitted on a chip.

But they have now become so small that electrical current can leak out of the transistors as heat, a problem that is evident at the current 90-nanometer process generation and is expected to get worse at the 65-nanometer process generation scheduled for introduction in 2005 and 2006. The number attached to the process generation refers to the width of the smallest circuit line within a chip.

Other chip-making techniques that go beyond simply shrinking the transistor include Intel's plans to integrate tri-gate transistors by the end of the decade to help control current leakage.

Also on Monday, IBM claimed it had built and demonstrated the world's smallest stable SRAM cell. IBM researcher Jack Hergenrother said the cells, which consist of six transistors, were half the size of the smallest experimental cell built to date, and 10 times as small as SRAM cells available today.

Chip companies generally build SRAM cells as test products for new manufacturing techniques or tools. SRAM is often used as cache memory, which improves the performance of a processor by storing frequently used data close to the processing unit.

The SRAM cells will also be presented next week at the IEDM meeting.

Tom Krazit writes for IDG News Service

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