IBM combines two semiconductor manufacturing techniques for fast transistors

News

IBM combines two semiconductor manufacturing techniques for fast transistors

By combining two semiconductor manufacturing techniques, IBM hopes to improve transistor performance by about half in the next three to five years.

The two techniques, strained silicon and silicon on insulator (SOI), have been brought together for the first time in a technique called strained silicon directly on insulator (SSDOI), IBM said.

Additionally, IBM has developed another way to increase transistor performance by combining different substrates on a single wafer, said Meikei Ieong, senior manager of exploratory device and integration at IBM Research.

In order to keep increasing the speeds at which current flows through a chip, designers have come up with different ways to reduce power leakage and increase the mobility of electrons within a circuit.

One such technique in use is SOI, which adds a thin oxide layer to a silicon wafer in order to insulate the circuit against power leakage.

AMD already uses this technique in building its Opteron server processor, and IBM has also used the technique for a few years.

Strained silicon, which is expected to appear on Intel's 90-nanometer chips, is a technique where a layer of silicon germanium is deposited on top of a silicon wafer, stretching the silicon atoms to allow electrons to flow faster through a circuit.

IBM's research allowed the company to use a layer transfer technique to apply both SOI and strained silicon to the same silicon wafer.

Researchers created a layer of strained silicon on top of a layer of silicon germanium, and then added an oxide layer atop that structure. That structure was then flipped over and placed on top of a second silicon wafer. This allowed researchers to remove the layer of silicon germanium at the end of the process, Ieong said.

By removing that layer of silicon germanium, IBM can improve the thermal conductivity of the wafer and eliminate a foreign material from the manufacturing process that adds complexity.

This technique will not be ready for production chips for another three to five years, Ieong said. It might make its debut on IBM's 65nm process technology.

Tom Krazit writes for IDG News Service


Email Alerts

Register now to receive ComputerWeekly.com IT-related news, guides and more, delivered to your inbox.
By submitting you agree to receive email from TechTarget and its partners. If you reside outside of the United States, you consent to having your personal data transferred to and processed in the United States. Privacy
 

COMMENTS powered by Disqus  //  Commenting policy