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PLC flash: The next generation or a mirage?

PLC could be productised within two years, but chip makers might not think it worth the effort. Will managing multiple voltages be more hassle than adding layers to existing flash?

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Storage manufacturers constantly work to improve capacity and cut costs. Nowhere is this more apparent than with flash storage, where capacities have risen from gigabytes to 20TB and more. Performance is way ahead of what’s possible with spinning disk, and cost per GB could overtake HDD soon.

Penta-level cell (PLC) flash is the latest generation of solid-state storage based around 3D NAND technology. It uses five bits per cell to store data, with the promise of larger volumes on a single chip and so – manufacturers hope – a lower cost per GB.

However, PLC flash means taking a number of compromises. These include reduced durability, more complex controllers and – as a result – lower performance. This is likely to limit the use cases for PLC flash, especially in its early years.

What is PLC flash?

The earliest generation of NAND flash storage used single-level cell (SLC) technology. This media, which is now largely obsolete, could only store one state, a 0 or 1, per cell. The industry then developed multi-level cell memory, which could store four states or switching outcomes.

Triple-level cells (TLC) increased the number of voltage switches to seven. QLC, with four bits per cell, has 16 states or 15 switches. This is currently the highest capacity NAND storage.

Currently, 30TB QLC SSDs are widely available from storage vendors, while some manufacturers – such as Pure Storage – ship proprietary 48TB drives.

This puts the capacity of flash ahead of even the largest conventional hard disk drives, and PLC flash could drive capacities much further. Alex McMullen, international CTO at Pure, predicts there will be systems with 300TB capacity “in the next 10 years”.

The development of PLC (and QLC) flash has been driven by improvements in storage controllers and software that manage the smaller voltages used to write data.

As 3D NAND has become the norm in chip architecture, manufacturers have added layers without making gates smaller, making QLC a practical proposal and opening the path to PLC flash.

Voltage challenges, errors and durability

Nonetheless, the move to higher capacity PLC flash poses challenges; chief among these is the number of voltage levels in the chip.

A PLC flash drive, with five bits per cell, holds 32 voltage levels, making the difference between voltages very small. This is trickier for the controller to read accurately, makes storage potentially less stable, and could impact I/O as controllers and error correction software are forced to work harder.

“The maximum increase in bit density from QLC to PLC will be 20% but will carry a much larger cost burden in regard to engineering around the expected complexity, lower performance and fragility of the medium,” says Pure’s McMullen.

With QLC, the difference between charge levels is about 6%, but with PLC that falls to 3%. This requires much more powerful error correction than MLC or TLC flash, for example.

“PLC has more bits in the same silicon area so it should be higher capacity, but [at the cost of] data reliability and retention,” says Joseph Unsworth, vice-president for emerging technology and trends, NAND flash, SSD, and SSA at Gartner. “We don’t know the NAND density or capacity because there are no commercially available products in the market today.”

Chip designers will also have to build in more redundancy. Already, with other types of flash, manufacturers add more capacity to modules to cover cells that wear out. This overhead is likely to be higher with PLC.

As yet, there are not any published I/O figures for PLC flash as manufacturers are yet to release samples, but storage vendors expect a performance hit – and then there are questions about how long PLC flash will last.

“Penta will be less durable. That is the undeniable mechanics of it. As the delta between each charge level becomes smaller, you have to programme more carefully, so it operates more slowly,” says Pure’s McMullen.

PLC use cases

Performance and the ratio between cost and capacity will determine where and how enterprises use PLC flash.

Early uses look set to include archiving and other long-term storage applications that do not depend on high write speeds or frequencies, but where capacity is important. This could extend to other areas that use vast amounts of data, such as machine learning training systems.

PLC flash is expected to be cheaper than QLC, although Gartner expects cost savings to be only around 10%, which is perhaps not enough to entice CIOs to switch.

Enterprise adoption will also depend on the durability of PLC flash modules. The earliest versions of QLC flash managed around 1,000 write/erase cycles. Current QLC chips have at least doubled that, but this compares with 100,000 cycles or more for the most durable designs based on more mature flash technologies.

Write/erase cycles matter less for long-term storage, however. And PLC flash is expected to be far more energy efficient than large-capacity spinning disks. Energy savings and a reduced carbon footprint could be what prompts enterprises to adopt PLC technology.

But the consensus among manufacturers and analysts is that large-scale PLC flash shipments are still at least two years away.

PLC and the future

PLC is not the only way manufacturers are looking to expand flash storage capacities.

Already, chip makers have demonstrated hexa and hepta-cell technologies at the prototype stage, with a hepta-cell flash cell will having 128 charge levels. A 10-level cell is theoretically possible, but the charge difference would be just 0.1%, and that’s a real engineering challenge.

Instead, storage manufacturers are looking to add layers to existing technologies, such as TLC and QLC. As Gartner’s Unsworth points out, a chip with a more advanced layer count will always have a cost and performance advantage over a chip with more levels but fewer layers, given the impact of additional levels on durability and controller design.

“It is conceivable that QLC is as far as we get, and we’ll go back to TLC with more layers,” says Pure’s McMullen. With chip makers’ roadmaps aiming to 500-600 layers, PLC is by no means the only option for the next generation of high-capacity flash storage.

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