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Pure Storage drips out more of its all-flash analytics FlashBlade

Pure lets more customers use its flash-based analytics platform FlashBlade, before the product aimed at high-throughput unstructured data is made generally available later in 2016

Pure Storage has announced the “directed availability” of its flash storage analytics platform, FlashBlade.

It aims for general availability by the end of 2016 for the hugely scalable platform built from flash and compute blades, with a target market of organisations that need high throughput rather than low latency/high I/O.

This is not a use of flash for rapid access transactional workloads and structured data, but for large volumes of unstructured data in analytics use cases – such as those found in genomics, oil and gas, video post-processing and chip development.

FlashBlade is made up of blades, each with Intel Xeon-based compute, memory, flash storage (8.8TB or 52.8TB), plus a custom-designed FPGA chip and six 40Gbps Ethernet ports. That gives up to 790TB in 4U of rack space, according to Pure Storage founder and CTO Jon Colgrove.

“At general availability we will limit it to 15 blades, but theoretically we could get about 8PB in a rack, 15PB with data reduction applied,” he said.

Directed availability follows a period of beta trials earlier in 2016, and sees a wider – but still closely supervised – customer distribution.

Protocols supported are object and file-access and are aimed at customers who want high throughput, especially for analytics workloads.

Colgrove explained that the special appeal of FlashBlade is in how the custom-designed controller chip makes best use of flash.

He said: “There's a lot of parallelism in flash operations, but SAS and SATA interfaces can't take advantage of it because flash doesn't look or act like a [spinning disk] HDD. So, we mounted NAND flash on a set of boards with an FPGA controller to exploit that parallelism and gain advantages in thoughput.”

Read more about flash storage and analytics

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  • X-IO comes out of stealth with Intel-backed Axellio that will see up to 0.25PB and 12 million IOPS from a 2U box using NVMe as an internal interconnect to speak natively with CPUs

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