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SSD write endurance: Will HP's memristor be the successor to flash?

Flash SSD write endurance faces increasing problems as the fabrication geometry shrinks to 10 nanometres and below. There appears to be only one solid candidate technology to succeed it, and it looks like HP holds the cards with memory resistor (memristor) technology.

Flash comes in MLC and SLC forms: single-level cell, with one bit per cell; and multi-level cell, with two, three or four bits per cell. Each bit addition to the cells lowers SSD write endurance in terms of the number of times it can be erased and written to, known as the P/E (programme/erase) cycle number.

SSD write endurance is the in-built limitation to increases in flash capacity, which relies on increasingly smaller geometries to squeeze more cells into a chip.

Samsung says SLC flash has a 100,000 P/E cycle number, two-bit MLC supports 10,000 writes and three-bit flash can sustain 1,000 before it gives up the ghost. We think this refers to sub-50 nm flash.

Meanwhile, Anobit says SLC flash made with 35 nm geometry has around 50,000 P/E cycles whereas two-bit MLC with the same geometry only has 3,000 cycle capacity. This is roughly in the same ballpark as the Samsung figures in terms of the drop in P/E cycle numbers from SLC to two-bit MLC. By extrapolation we could say that three-bit MLC would have 300-500 P/E cycles, rendering it unusable.

Sub-30 nm NAND has lower endurance than 35 nm chips, and sub-20 nm flash has lower endurance still. We can say that each 10 nm drop in process geometry lowers the P/E cycle number by half. Using this rule of thumb, sub-20 nm SLC NAND will support 25,000 P/E cycles, two-bit sub-20 nm NAND 2,500 and three-bit 250. Going to sub-10 nm would produce 12,000 P/E cycle SLC, 120 for two-bit MLC and 12 for three-bit MLC. This is a fool's game obviously.

What all this tells us is that increases in flash capacity are going to stop happening unless controllers can do miraculous things with the degraded signals that come from worn-out flash. Anobit claims its technology can do this, by the way, amplifying endurance by a factor of 40 with its second-generation technology.

Setting that aside, what are the candidate technologies to succeed flash storage?

Firstly there is phase-change memory, which stores bits as different resistance levels in a chalcogenide material whose state alternates between a poly-crystalline one and an amorphous one by applying electricity to heat a cell. It is meant to be non-volatile like flash and as fast, roughly speaking, as DRAM, and also bit-addressable. Flash is only page-addressable, leading to complications when altering data already written to flash. 

Micron and Samsung are the two companies developing phase-change memory, and both face problems productising it. Neither has a shipping 1 Gb chip, and both use technology in the 40-60 nm range, behind that of flash, which is currently using mid-30s nm process geometry and heading into the 20s.

Then there is CMOx (conductive metal oxide) technology, which is being developed by Unity Semiconductor and is said to be four times denser than flash and five to 10 times faster at writing data. How this works takes you into brain-ache territory; it involves a resistance change element and quantum mechanical tunnelling, which cause oxygen ions to move between a conductive metal oxide and an insulating one.

Apparently Unity is working with Micron to commercialise this technology. It has been in development for eight years. Micron is working on phase-change memory as well so is not totally committed to CMOx. Unity is a memory technology company, and not a production company, so it is utterly dependent upon licensing its technology to others to productise. The deal with Micron was announced in January, and it is possible product could result by 2014.

Meanwhile, IBM has its racetrack memory idea. This is nanoscale technology with magnetic domains: tiny, tiny entities with north and south poles that move along a nanowire by a spin-polarised electric current to and from a reading station. This is known as spintronics, or spin-transfer torque RAM. Hynix was working in the area and had licensed technology from Grandis. Fujitsu and Hitachi also have STT-RAM projects. There is no realistic indication about when any product might be developed from this bleeding-edge research, and Hynix appears to have abandoned it. You should never write off IBM, but it's a long way from the research lab to the fabrication plant floor.

HP has its own gee-whiz memory candidate in memristor technology. A memristor is said to be a fourth fundamental electrical circuit element along with the resistor, capacitor and inductor.  HP has found a way to stack two-dimensional memristor structures to produce a three-dimensional chip with high capacity. The company has said it could build a memristor device with a density of 20 GB per square centimetre by the close of 2013, twice as dense as flash would be then. It says its technology uses less power than phase-change memory, which needs to heat its chalcogenide material to cause a state change, and switches bit state faster.

With HP as the only vendor of substance working on this technology, we might be concerned, no matter much respect we have for HP's technological prowess. However, this is where Hynix pops up again, having signed a deal with HP to jointly produce a memristor technology product called Resistive Random Access Memory (ReRAM). Bits are stored as different resistance levels in the chip cells, and these levels are changed by applying a voltage to the cells. ReRAM is non-volatile, near to DRAM in switching speed, bit-addressable and doesn't suffer from flash endurance problems.

ReRAM product could appear, as HP claims, by the end of 2013. If it does, if it lives up to the HP-set expectations and if NAND's endurance problems haven't been solved by innovative controller technology, then HP could find itself licensing memristor technology and having a considerable revenue stream as a result -- unless the CMOx idea from Unity Semiconductor and Micron comes up trumps.

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This was first published in March 2011

 

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